1. Field of the Invention
The present invention relates to a structure of a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a semiconductor device using an SOI substrate and a method of manufacturing the same.
2. Description of the Background Art
FIG. 47 is a cross section showing a structure of a semiconductor device using an SOI substrate in accordance with a first background art. As shown in FIG. 47, the semiconductor device of the first background art comprises an SOI substrate 101 having a multilayered structure in which a silicon substrate 102, an insulating layer 103 and a silicon layer 104 are layered in this order. In an upper surface of the silicon layer 104, a plurality of isolation insulating films 105 of partial-trench type are selectively formed. In an element formation region of the 501 substrate 101 defined by the isolation insulating films 105, an NMOS transistor (hereinafter, referred to as “NMOS”) is formed. The NMOS has an n+-type source region 109s and an n+-type drain region 109d which are formed in the silicon layer 104 and paired with each other with a p-type channel region 110 interposed therebetween. Further, the NMOS has a gate structure which is formed on the channel region 10 and has a multilayered structure in which a gate insulating film 106 and a gate electrode 107 are layered in this order and sidewalls 108 formed on side surfaces of the multilayered structure. Furthermore, in the silicon layer 104, a p+-type body region 111 is selectively formed.
An interlayer insulating film 120 is formed on the NMOS, the isolation insulating film 105 and the body region 111. On the interlayer insulating film 120, wires 113 and 117 are selectively formed. In the interlayer insulating film 120, a contact hole 112 filled with a conductive plug therein is selectively formed to electrically connect the wire 113 and the drain region 109d. Further, in the interlayer insulating film 120, a contact hole 116 filled with a conductive plug therein is selectively formed to electrically connect the wire 117 and the source region 109s. 
An interlayer insulating film 121 is formed on the interlayer insulating film 120, and a power supply line 115 and a ground line 119 are selectively formed on the interlayer insulating film 121. In the interlayer insulating film 121, a contact hole 114 filled with a conductive plug therein is selectively formed to electrically connect the power supply line 115 and the wire 113. Further, in the interlayer insulating film 121, a contact hole 118 filled with a conductive plug therein is selectively formed to electrically connect the ground line 119 and the wire 117.
FIG. 48 is a plan view showing a structure of a semiconductor device using an SOI substrate in accordance with a second background art. As shown in FIG. 48, the semiconductor device of the second background art comprises two CMOS transistors (hereinafter, referred to as “CMOS”) 140 and 141 formed adjacently to each other with the isolation insulating film 105 of partial-trench type interposed therebetween.
The semiconductor device of the first background art shown in FIG. 47, however, has the following problem. FIGS. 49 and 50 are timing charts used for explaining the problem of the semiconductor device in accordance with the first background art. In a logic circuit using the semiconductor device of FIG. 47, if a reference clock rises when an input potential is “H”, an output potential shifts from “L” to “H” (for example, time T1 of FIG. 49 and time T3 of FIG. 50) and if the reference clock falls when the input potential is “L”, the output potential shifts from “H” to “L” (for example, time T2 of FIG. 49 and time T4 of FIG. 50). As shown in FIG. 47, in the semiconductor device of the first background art, the power supply line 115 and the ground line 119 are formed above the body region 111. Therefore, when the potentials of the power supply line 115 and the ground line 119 are affected by the effect of some external noise to vary, the potential of the body region 111 also varies due to capacitive coupling. The variation in potential of the body region 111 appears as an input noise 130 in an operation of the above logic circuit.
At this time, as shown in FIG. 49, if the operating frequency of the logic circuit is low, ranging from about several KHz to several MHz, and the cycle of the reference clock is sufficiently longer than the waveform of the noise 130, the operation of the logic circuit is hard to be affected by the noise 130. As shown in FIG. 50, however, if the operating frequency of the logic circuit is high, about several GHz, the operation of the logic circuit is likely to be affected by the noise 130. In the case of FIG. 50, the output potential at time T5 shifts from “L” to “H” and the output potential at time T6 shifts from “H” to “L”, and as a result a wrong output pulse 131 is generated.
Thus, the semiconductor device of the first background art, which is likely to be affected by variation in potential of the body region and potential of the power supply line and the ground line, has a problem that malfunction is likely to occur as the operating frequency of the semiconductor device becomes high.
The semiconductor device of the second background art of FIG. 48 has the following problem. FIG. 51 is a cross section used for explaining the problem of the semiconductor device in accordance with the second background art. FIG. 51 corresponds to a cross-sectional structure of the semiconductor device of FIG. 48 taken along the line L100, and a left-side transistor of FIG. 51 corresponds to the NMOS included in the CMOS 140 and a right-side transistor corresponds to the NMOS included in the CMOS 141.
It is generally known that an operation of a transistor is likely to be affected by temperature and a current flowing in the transistor is reduced as the ambient temperature gets higher. In the semiconductor device of FIG. 48, it is assumed that the CMOS 140 has a relatively high operating threshold voltage and a large calorific value with large current flow while the CMOS 141 has a relatively low operating threshold voltage and a small calorific value. In this case, the heat generated in the CMOS 140 is conducted to the CMOS 141 through the silicon layer 104 below the isolation insulating film 105 as represented by an arrow 150 of FIG. 51. Then, the heat works to reduce the current in the CMOS 141, making the operation of the CMOS 141 unstable. As a result, malfunction occurs to deteriorate the circuit characteristics especially in a circuit whose operation sensitively depends on magnitude of current such as an analog circuit and an RF circuit.
Thus, in the semiconductor device of the second background art, if two semiconductor elements having different calorific values are formed adjacently to each other, the heat generated in one of the semiconductor elements affects the operation of the other to disadvantageously cause a malfunction.